As it is known, PCM memories represent a new generation of embedded memories, in which the features of materials having the property of switching between phases having different electrical characteristics are exploited to store information. These materials may switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase, and resistivity of a considerably different value, which consequently correspond to a different value of a datum stored, are associated to the two phases.
For example, the elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), called chalcogenides or chalcogenic materials, may advantageously be used in the manufacturing of phase-change memory cells. In particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having a chemical composition Ge2Sb2Te5) currently finds a wide use in such memory cells.
Phase changes may be obtained by local increase of the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as “heaters”), arranged in contact with respective regions of chalcogenic material.
Access elements, in particular MOS transistors, are connected to the heaters, and selectively enable passage of a programming electric current through a respective heater. This electric current, by the Joule effect, generates the temperatures required for phase change. In particular, when the chalcogenic material is in the high-resistivity amorphous state (the so-called RESET state), it is required to apply a current/voltage pulse (or an appropriate number of such pulses) of a duration and amplitude such as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Instead, when the chalcogenic material is in the SET state, it is required to apply a current/voltage pulse of an appropriate duration and with a high amplitude for causing the chalcogenic material to return into the high-resistivity amorphous state (RESET state).
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause a relevant heating thereof, and then reading the value of the current flowing in the memory cell (which is once again selected by the respective access MOS transistor). Since the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and thus to identify the datum stored in the memory cell.